The present invention is directed to random access memory devices, and more specifically to means for reducing the time it takes for data written into a memory cell to thereafter be available for read out from the memory.
In conventional memory systems, the interval of time needed to complete a write operation is determined by the time it takes for the data signal being written into the memory to propagate through the memory plus the time it takes for the memory cell or cells in which the data is being written to change state, i.e, its roll-over time. The time that a memory user must wait until this data can be accessed for read out of the data is generally termed the write recovery time of the memory (TWR). A number of procedures are known in the art for reducing both the propagation delay in the memory and the roll-over time of a memory cell. For example, the propagation delay can be reduced by minimizing lead lengths in the memory system. Memory cell switching can be speeded up by minimizing the inherent capacitances which exist in the memory cell transistors, by reducing the resistance of bias resistors in the cell, etc.
One of the tradeoffs in designing such memory cells is that to get low power, you want the bias resistors in the cell to be large. If high speed is desired, however, small resistors are needed. Combining small resistors with minimized parasitic capacitances in the transistors used in the memory cells reduces the RC time constant effects of these elements. The drawback of various process improvements which attempt to minimize parasitic and junction capacitances in a memory cell is that they tend to increase the overall cost of the memory system. What is therefore needed is a memory system that does not require unusual processing, is designed to operate at low power, and at the same time provides a memory system which has a very fast write recovery time.
This problem is more of a concern in certain of the more recent memory systems, since the memory user of such memory systems is no longer required to wait a full memory cycle time before beginning a read operation after a write operation has been completed. For many memory systems, all the memory designer needed to do was to make sure that the write recovery time was less than the time it took the user to address the same memory cell during the next read cycle. More recent users, however, have insisted on systems that give them the ability to do a read operation in the same cycle as the write operation. In these latter systems, write recovery times on the order of five to ten nanoseconds or less are required.
Consequently, an object of the present invention is to minimize the write recovery time of memory cells in a memory during a write operation so as to enable a user to perform a subsequent read operation of data written to that cell or cells as soon as possible after the data has been written. That is, the present invention is designed to substantially eliminate the memory's write recovery time, the interval that exists between the time data is presented to a memory cell, is stored in the memory cell, and thereafter propagates through the cell's sense amplifier and out to the output data lines of the memory.